| Architecture |
SPARC V8 Architecture |
| Bit Width & Performance |
32-bit High-performance Radiation-hardened Microprocessor |
| On-chip Memory & Core Hardware |
256KB on-chip memory; integrates hardware multiplier/divider, independent instruction cache and data cache, double-precision floating-point processing unit |
| System-level Feature |
Adopts system-level fault tolerance |
| External Memory Support |
Supports DDR2, and 8/16/32-bit wide external memory data access |
| Integrated Peripheral Interfaces |
Integrates multiple peripheral interfaces including 10/100/1000Mbps Ethernet MAC, DMA, SPI, I²C, PWM, timer, counter, watchdog, interrupt controller, PCI, UART and GPIO |
